Hardware–Algorithm Co-Optimization of Weight-Update Protocols in Oxide-Based Synaptic Transistor Arrays for Neuromorphic Systems
TL;DR
This work provides an experimentally calibrated behavioral simulation platform and concrete algorithm-hardware co-design guidelines for future neuromorphic hardware, prioritizing synaptic devices with long-term depression > 0, a moderately elevated Gmin, and asymmetric resource allocation toward LTD-side optimization.
Abstract
The transition from single-device characterization to array-level simulation remains a critical challenge in the development of three-terminal synaptic transistors for neuromorphic computing, as most existing simulation studies either extract parameters from a single representative device and apply them uniformly, or rely on weight-update strategies originally designed for two-terminal memristors. Here, we establish an experimentally calibrated behavioral simulation framework based on differential conductance-pair mapping (W = G+ − G−, where G+ and G− denote the conductances of the positive and negative devices of each pair), integrating exponential long-term potentiation/depression (LTP/LTD) update rules with a posteriori screening mechanism (isValid) to systematically investigate how update polarity, step size, nonlinearity, and conductance boundaries regulate network computational efficiency. Through comprehensive simulation on the Neural Circuit Policies network, we demonstrate that the update direction must strictly align with the matrix’s role: the G− channel requires unidirectional long-term depression inhibition, while the G+ channel can be frozen or bidirectionally updated. The optimal G−LTD and G+G−LTD strategies achieve accuracies of 0.9208 and 0.9481, respectively. Furthermore, we reveal a unique nonlinear gain effect under long-term depression > 0, where accuracy increases monotonically with nonlinearity level up to 0.9419. Device specification criteria are established: LTP-dominant updates favor large Gmax, while LTD-dominant updates favor high Gmin, with the G−LTD and G+G−LTD strategies showing accuracy fluctuations within ±0.005 across the tested boundary variations. Finally, the array-level implementation is validated through a functional-correctness check and device-parameter ablation experiments on a 23,715-weight array (47,430 differential conductance elements). This work provides an experimentally calibrated behavioral simulation platform and concrete algorithm-hardware co-design guidelines for future neuromorphic hardware, prioritizing synaptic devices with long-term depression > 0, a moderately elevated Gmin, and asymmetric resource allocation toward LTD-side optimization.