TL;DR
Experimental analysis of verification parameters in a Constrained Random Verification (CRV) -based cross-level setup shows that different coverage metrics exhibit distinct saturation behaviors as verification parameters are varied.
This work presents a comprehensive analysis of contemporary hardware fuzzing techniques applied across three major abstraction layers: Instruction Set Architecture (ISA), microarchitecture, and Register-Transfer Level (RTL). Our study examines key factors including input stimulus quality, mutation strategies, feedback...
Microcontroller (MCU)-based devices are increasingly pervasive, making efficient, scalable firmware security analysis critical. Recent firmware re-hosting work enables automated vulnerability assessment, yet two gaps remain. First, existing tools are evaluated on limited, heavily overlapping datasets, undermining the g...
A metamorphic testing based evaluation method and a companion benchmark to measure the effectiveness of LLM-aided RTL code optimization show that LLM-aided methods effectively optimize logic operations and data paths, achieving lower or stable wire counts and area with delays near baseline.
A Sail-guided FP-RVVTS flow that uses Sail RISC-V as an executable RISC-V specification for differential verification of RISC-V Floating-Point (FP) implementations, from Instruction Set Simulator s to Register Transfer Level (RTL) designs.
PerfReasoning is introduced, a benchmark that evaluates LLMs both as direct performance reasoners and as generators of analytical performance-model code, exposing the gap between plausible architectural reasoning and reliable performance-model construction.
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