This work presents a comprehensive analysis of contemporary hardware fuzzing techniques applied across three major abstraction layers: Instruction Set Architecture (ISA), microarchitecture, and Register-Transfer Level (RTL). Our study examines key factors including input stimulus quality, mutation strategies, feedback mechanisms, target platforms, reference models, and achieved coverage. We find challenges, goals, and design trade-offs vary significantly across abstraction layers. We further identify several unmet needs in current hardware fuzzing practices, such as intelligent input generation, reliable and scalable golden reference models, expressive feedback channels, and cross-layer integration. Building on these insights, we outline future research directions, including hybrid fuzzing frameworks, AI-assisted test generation, scalable reference models, standardized evaluation metrics and benchmarks, and human-in-the-loop automation for guided exploration and analysis. Together, they aim to unlock efficient, reliable, and comprehensive hardware verification solutions.
PerfReasoning is introduced, a benchmark that evaluates LLMs both as direct performance reasoners and as generators of analytical performance-model code, exposing the gap between plausible architectural reasoning and reliable performance-model construction.
Da Zhao, K. Sankaralingam, Christos Kozyrakis et al.· 0 citations
Janus is presented, an LLM-assisted framework that synthe-sizes custom instructions integrated into the Ibex RISC-V core while keeping correctness outside the agent, demonstrating a practical path for using LLMs to explore ISA specialization without making the agent part of the trusted correctness boundary.
Experimental analysis of verification parameters in a Constrained Random Verification (CRV) -based cross-level setup shows that different coverage metrics exhibit distinct saturation behaviors as verification parameters are varied.
Sallar Ahmadi-Pour, Luca M. ̈uller, Rolf Drechsler· 0 citations
A metamorphic testing based evaluation method and a companion benchmark to measure the effectiveness of LLM-aided RTL code optimization show that LLM-aided methods effectively optimize logic operations and data paths, achieving lower or stable wire counts and area with delays near baseline.
Zhi-Hao Xu, Bi-Xin Li, Ran Yan et al.· ACM Transactions on Reconfig...· 0 citations
SynaSpace is a behavior-driven configuration optimization framework for fault detection in logic synthesis tools that focuses on synthesis behavior coverage to guide configuration search, by constructing behavioral representations through joint analysis of synthesis logs and gate-level netlists.
Pei-Yu Zou, Xiao-Chen Li, Yijia Meng et al.· ACM Transactions on Design A...· 0 citations
FinHardBench, a benchmark of 33 financial computing tasks, is presented together with three experiments that mirror the real-world FPGA iteration cycle: generating new modules from specifications, tuning system-level configurations across a 6-stage trading pipeline, and adapting existing modules to specification change...
Weimin Fu, He-Jia Zhang, Ming-Hao Shao et al.· 0 citations
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