Rethinking LLM-aided RTL Code Optimization Via Timing Logic Metamorphosis
TL;DR
A metamorphic testing based evaluation method and a companion benchmark to measure the effectiveness of LLM-aided RTL code optimization show that LLM-aided methods effectively optimize logic operations and data paths, achieving lower or stable wire counts and area with delays near baseline.
Abstract
Register Transfer Level (RTL) code optimization is critical for meeting performance and power budgets in Field Programmable Gate Array (FPGA) design. Traditional approaches depend on expert knowledge or heuristics, which are time consuming and error prone. Therefore, recent research has explored using Large Language Models (LLMs) for RTL code optimization and providing initial evidence of their potential. However, the capabilities and limitations of LLMs in RTL code optimization have not been systematically assessed, especially for RTL with complex timing logic. Moreover, these studies cannot distinguish whether improvements come from genuine reasoning or merely reproducing memorized patterns from training data. To address these problems, we present a metamorphic testing based evaluation method and a companion benchmark to measure the effectiveness of LLM-aided RTL code optimization. Our key idea is that optimization effectiveness should be consistent across RTL descriptions that are semantically equivalent. We first build a benchmark suite covering four domains (logic operations, datapaths, timing control flow, and clock domains). We then apply domain specific transformations to produce semantically equivalent RTL code with different code forms. We assess each method by applying it to both the original and the transformed code, synthesizing them with the same flow, and comparing the synthesis results. Through extensive experiments, our results show that LLM-aided methods effectively optimize logic operations and data paths, achieving lower or stable wire counts and area with delays near baseline. For timing control flow and clock domains the gains are limited and structural ratios often rise. Larger code size also increases the chance of incorrect rewrites, especially in timing and cross domain designs. We further explore the application of prompt engineering include few shot examples and Chain of Thought (CoT) to improve RTL code optimization. Based on these results we discuss practical directions and give concrete suggestions for using LLMs in RTL optimization.