Adaptive Precision Hierarchical Vedic Multiplier with CSA-Based 64-Bit Optimization for Low-Power FPGA Applications

Abstract

In this paper, an energy-efficient Vedic multiplier design is presented through runtime-adaptive hierarchy. In the proposed architecture, the Urdhva-Tiryakbhyam Vedic algorithm has been implemented recursively from 2x2 to 32$\times$32 bit multiplication in a modular hierarchical fashion. In addition, the multiplier has been extended to support 64-bit multiplication using a Carry Save Adder (CSA) based partial product reduction stage [8], [10], which minimizes the accumulation delay, switching activity, and dynamic power consumption in the arithmetic circuitry. Moreover, the framework can support runtime precision adaptation in 8, 16, 32, and 64-bit precision modes [4], [15], allowing the arithmetic operation to be performed only in the required precision mode, thus minimizing the hardware switching activity. The system has been designed in Verilog HDL and has been implemented on the Xilinx Spartan-7 XC7S50 FPGA using the Vivado 2023.2 environment. In the design, the input operands are stored in the hardware in the 64-bit precision mode, while the output results are monitored using UART-based serial communication using a Python serial console. In the experimental results, the system has been shown to consume lower power in the lower precision modes compared to the results obtained in the 64-bit precision mode, while the design has been shown to improve the performance compared to the conventional Vedic accumulation architecture in the 64-bit precision mode.