A Power-Aware 64-bit Hybrid Multiplier using Vedic Arithmetic and Wallace Tree for High-Performance Filter Applications

A Low-Power 4-Bit Vedic Multiplier Utilizing Modified Gdi and Sapon Techniques

In Digital Signal Processing (DSP) and other computational applications, the multiplier is a fundamental building block and efficient design of the multiplier has a significant impact in the enhancement of the performance of Integrated Circuits (ICs). Vedic Multipliers are one of the different types of multiplier archi...

Scalable Modified Vedic Multiplier Using HSCG-SCG-CSLA for High-Speed FPGA Arithmetic

High-speed multiplication is a dominant requirement in digital signal processing, image processing, cryptography, and embedded arithmetic units. This work develops a scalable modified Vedic multiplier based on the Urdhva-Tiryagbhyam vertical-and-crosswise principle and replaces conventional carry-intensive final additi...

Design and Power Optimization of Array Multiplier using Brent-Kung Architecture

An Optimized Carry Increment Adder Architecture for High-Performance and Low-Power Processors

Low Power Hybrid Approximate Adder using BSPAA for Error Tolerant Applications

Approximate computing is a promising way to improve energy efficiency and speed in applications where precise computation may not be necessary, like applications involving image processing. Within the domain, arithmetic circuits, especially adders, significantly influence the overall power usage and timing constraints....

Design and FPGA implementation of reversible vedic multipliy and accumulate unit for cryptography applications