Aug 2026· 2026 2nd International Conference on Electronic Information, Computer and Aerospace Remote Sensing (EICARS)· pp. 344-350· 0 citations· 15 references
Abstract
The application of Large Language Models (LLMs) to embedded firmware development presents unique challenges: domain-specific register-level programming, stringent resource constraints, and the absence of structured validation mechanisms. Existing approaches using direct LLM-assisted coding suffer from hallucinated library functions, incorrect register configurations, and low compilation success rates, particularly for resource-constrained microcontrollers. This paper presents a three-layer framework that integrates DeepSeek-based code generation with an automated cross-compilation validation pipeline and hardware-in-the-loop (HIL) testing. The framework comprises an LLM integration layer with a local protocol proxy bridge, a three-stage code validation pipeline (static analysis, cross-compilation, and HIL testing), and a domain-specific prompt engineering module. Empirical evaluation across five benchmark tasks on ESP32-S3 and STM32F103 platforms demonstrates that the framework reduces development time by 53.7% on average compared to manual development (p < 0.001, Cohen's $\mathrm{d} = 2.34)$, while achieving 89.2% functional correctness—a 16.7 percentage point improvement over direct LLM-assisted coding $(\mathrm{p}<0.01$, Cohen's $\mathrm{d}=1.18)$. Error analysis reveals that hallucinated API calls are reduced by 77.2% and logic/timing errors by 74.1%. Compared to the recently proposed AutoEmbed system, our framework achieves comparable end-toend success rates (89.2% vs. 86.5%) while providing explicit cross-compilation and HIL validation stages absent from AutoEmbed's auto-programming approach. The framework leverages DeepSeek-V4-Flash for code generation, achieving substantial cost reduction compared to GPT-4-based alternatives based on published API pricing, making it economically viable for iterative embedded development workflows.
Large Language Models (LLMs) are increasingly applied in hardware design automation, demonstrating strong potential in generating and understanding hardware description languages. However, most existing benchmarks focus on Verilog, with limited evaluation of VHDL, which remains widely used in industry and academia for...
P. Vijayaraghavan, Akul Malhotra, A. Jadhav et al.· 0 citations
FPGAgent is the first task-specification-to-executable HLS generation framework experimentally validated on a well-established benchmark, and the value of end-to-end validation is demonstrated.
Tian-Yun Wang, Wenjie Wang, Jian-Guo Yao et al.· 0 citations
Large language models (LLMs) can generate register-transfer-level (RTL) code from natural-language specifications, but compilation alone does not establish structural completeness, functional correctness, or implementation efficiency. This paper presents a framework for evaluating LLM-generated RTL beyond compilation,...
Hepziba Susan, R. ShivaranjaniG, Malik Imran et al.· 1 citation
Large Language Models (LLMs) are increasingly being explored for register-transfer-level (RTL) generation, hardware verification, debugging, and design automation tasks. Unlike traditional electronic design automation (EDA) workflows that rely heavily on formal methods and handcrafted heuristics, LLM-based systems intr...
S. Ahir, Alex Doboli, S. Doboli· 2026 IEEE 4th Conference on...· 0 citations
Field-Programmable Gate Array (FPGA) synthesis and simulation tools, such as Vivado, Quartus, Yosys, and Icarus Verilog, are key components of Electronic Design Automation (EDA) toolchains, translating high-level Hardware Description Language (HDL) designs into low-level gate netlists. However, defects in these compile...
He Jiang, Wen Zhao, Shi-Kai Guo et al.· Proceedings of the ACM on So...· 0 citations