Jul 2026· International Conference on Optical Communications and Networks· pp. 1-3· 0 citations· 11 references
Abstract
High-precision and large-capacity network delay emulation is essential for algorithm validation and system testing in cloud computing, satellite communications and vehicular IoT. This paper proposes a novel FPGA-based high-bandwidth delay emulation method, which buffers packets in on-chip Ultra RAM, maps packet identifiers to RAM addresses via a single-cycle 32-bit parallel CRC32 hash, and schedules packets by target egress timestamps using a Push-In First-Out (PIFO) mechanism. Experiments confirm that the system achieves lossless emulation of 1.5 ms network delay at 10 Gbps line rate.
Two open-source tools and open latency data sets are presented for simulating and emulating the characteristic port-to-port delay of logical 5G TSN bridges.
Lucas Haug, Frank D. ̈urr, Simon Egger et al.· 2 citations
Programmable network data planes enable limited in-network computation, but most prior work has focused on narrow primitives or small-scale prototypes. This paper demonstrates real-time processing of high-dimensional image streams at near-terabit rates on the FABRIC testbed using programmable switches. We design a ligh...
G. Sankaran, I. Torres, Seena Vazifedunn et al.· International Conference on...· 0 citations
Evaluation results show that, while these mechanisms consume a small amount of link bandwidth, CBFC can greatly reduce receive buffer utilization, and LLR can substantially mitigate network performance degradation caused by packet corruption.
Kefei Liu, Ruixue Wang, Tianrun Jiang et al.· Conference on Applications,...· 1 citation
An open-source testing framework for IEEE 802.11p cards is developed and the performance of Unex DHXA-222 cards is characterized in terms of throughput and packet loss, especially when different traffic classes, hence access categories, are selected.