A 12-CNOT Double Qubit Excitation Gate

An entangling gate for dual-rail erasure qubits

Quantum error correction (QEC) will likely be required to realize the full potential of quantum computing, but comes with daunting hardware overheads and demands low gate errors on the physical qubits1, 2, 3–4. These requirements can be eased by engineering qubits with a strong error hierarchy, in which the most common noise channels are also the easiest to correct. Erasure qubits can achieve this when detectable leakage errors out of the computational subspace dominate over the residual Pauli errors5, 6, 7, 8, 9, 10–11, resulting in higher thresholds and improved scaling with code distance5,12,13. In practice, these advantages come to fruition only if the error hierarchy is preserved as much as possible throughout all gates and operations. Here we design and realize a two-qubit entangling gate for dual-rail cavity qubits, a type of erasure qubit encoded in a pair of superconducting microwave cavities7. Our experimental demonstration confirms that the error hierarchy is largely preserved during the gate. The gate is fast (about 500 ns duration) and shows low erasure rates of approximately 0.5% per gate, remaining Pauli errors below 0.1%, and a strong bias towards dephasing errors, in which bit-flips are practically non-existent at the 10−6 level. These results enable a faster path to error-corrected systems that rapidly suppress errors as they scale; a claim we support with our detailed surface code simulations. A fast, low-error entangling gate for dual-rail cavity erasure qubits preserves a strong error hierarchy, advancing scalable quantum error correction with substantially improved fault-tolerant performance.

On the Experimental Determination of Nonlocal Characteristics of Two-Qubit Gates

In this paper, we discuss the experimental determination of the nonlocal characteristics of two-qubit gates. Based on the recently derived expressions for the entangling power and gate typicality of two-qubit gates, we construct two-qubit quantum circuits to measure the entangling power and gate typicality of the two-qubit gates, which are generated by the elements of the su(4) Cartan subalgebra. These elements describe the native interactions in many quantum processors. Hence, these circuits can be used to determine the nonlocal characteristics of native gates of many quantum processors. In each circuit, the native gate is applied twice. In addition, each circuit consists of at least one CNOT gate. A set of six two-qubit circuits is constructed to measure the entangling power. The number of circuits is further reduced to three by increasing the nonlocal resources (the number of CNOT gates). To measure the gate typicality, a set of three two-qubit circuits is constructed. Measurement of gate typicality requires more nonlocal resources than the measurement of entangling power.

Towards logical entanglement creation in trivalent planar architectures

Low-overhead quantum error-correction schemes are essential for enabling quantum computation on registers containing multiple logical qubits. For planar architectures with limited nearest-neighbor qubit connectivity, the surface code has emerged as the leading paradigm. Recent theoretical and experimental work has shown that a physical-qubit connectivity of degree three is sufficient to implement fault-tolerant quantum error correction. In this work, we study lattice surgery in the context of such trivalent architectures and introduce scalable circuit constructions to implement it. Compared with the four-valent measurement scheme, the trivalent lattice-surgery protocol reduces the required resources by $\mathcal{O}(d)$ qubits out of a total qubit count of $\mathcal{O}(d^2)$ and by $\mathcal{O}(d)$ two-qubit gates out of a total two-qubit gate count of $\mathcal{O}(d^3)$. We benchmark the logical fidelity of both lattice-surgery schemes in terms of experimentally realistic simulations targeting an implementation with a fluxonium qubit based architecture and find a potential improvement of up to $\approx25\%$ for distance-three. These results open a way for scalable planar trivalent qubit architectures to host a surface-code-based logical quantum processor.

Novel SMT Encoding for Quantum Circuit Optimization

Clifford Circuit Synthesis for Distributed Quantum Architectures with Arbitrary Network Topology

This work considers the case where both non-local and local connectivity may be arbitrarily restricted, and gives an asymptotically optimal synthesis method for distributed CNOT and Clifford circuits, based on block-matrix Gaussian elimination.

Experimental demonstration of the Quantum Fourier Transform on up to 100 qubits using a convolutional compilation strategy

We present and experimentally validate the `Convolutional QFT': a constructive compilation strategy for the Quantum Fourier Transform (QFT) subroutine on a linear nearest neighbor (LNN) qubit topology. We first introduce a novel strategy that compiles the $n$-qubit QFT onto an LNN topology using only $n^2 - n$ $CX$ gates, matching requirements of a direct compilation on an all-to-all architecture. We then derive the convolutional variant used in our experiments, which requires an additional two $CX$ gates in total, and is realized via a compact, translation-invariant kernel circuit gadget that traverses a quantum register. We demonstrate the power of the convolutional compilation strategy on the IBM Quantum Platform by executing QFT benchmarking circuits. We measure a process fidelity of 11.4% at 50 qubits, and 1.8% at 80 qubits. The correct output state remains clearly distinguishable above background noise up to 100 qubits. These results constitute the largest experimental QFT demonstrated on any quantum computing hardware to date.