Optimized 64-Bit Double-Precision FMA with Robust Exception Handling

Abstract

As scientific computing moves closer to exascale performance, it has become more and more important to get high numerical accuracy and computational efficiency in floating-point op-erations. For big simulations, data analysis, and scientific modelling, high-precision arithmetic is necessary because small rounding errors can spread and make results less reliable. This work pre-sents an optimized 64-bit fused multiply-add (FMA) architecture that combines multiplication and addition into one operation, which cuts down on rounding errors and overall error. The design in-cludes fast exponent processing, precise operand alignment, and simplified normalization to make sure that double-precision calculations are accurate and faster. The architecture not only improves performance, but it also handles all kinds of unusual floating-point conditions, such as nan, infini-ty, zero, overflow, underflow, and subnormal numbers, before doing the main arithmetic opera-tion. To make the system more energy efficient, an operand isolation technique is built into the design to cut down on unnecessary switching activity. This lowers dynamic power use without affecting numerical accuracy. Verilog HDL is used to describe the architecture, and functional software simulations are used to check that it follows IEEE-754 double-precision rules and han-dles exceptions correctly. The evaluation results show that the fused implementation increases nu-merical accuracy and computational efficiency while using less power than traditional non-fused designs. In general, the proposed FMA unit is a strong and flexible solution for high-performance computing applications.