BHARAT-TPM: Micro-Architecture Design of AXI Enabled HMAC SHA-3 Hardware Accelerator for a RISC-V Trusted Platform Module

Abstract

Trusted Platform Modules (TPMs) have become essential components of contemporary hardware security, and implementations must include cryptographically robust algorithms such as SHA-3 and HMAC. Dedicated hardware accelerators for these algorithms are needed for high performance in TPM operations, including key derivation, authorization, attestation, and platform state extensions. This paper presents an AXIenabled multi-variant HMAC-SHA-3 hardware accelerator integrated into an indigenous RISC-V based TPM, named BHARAT-TPM. The proposed design is capable of calculating the SHA-3 or HMAC-SHA-3 digests for variants 224, 256, 384 and 512 of the SHA-3 hash function family. The design is also enabled with an AXI-4 interface for seamless integration into a RISC-V based TPM where it can be accessed using memory mapped registers. The proposed accelerator is implemented in Verilog RTL and verified u sing N IST t est v ectors. T he a ccelerator has also been integrated into BHARAT-TPM and prototyped on the Xilinx Virtex VCU118 FPGA board and validated by running TCG TPM2.0 commands, ensuring system-level functionality. The proposed architecture achieves a peak throughput of 5412.88 Mbps for SHA-3 and 2339.76 Mbps for HMAC operation, demonstrating capability for high-speed TPM based applications.