Sep 2026· Journal of Integrated Circuits and Systems· Vol 21· 1 citation· 3 references
TL;DR
The results indicate that no single technique is universally superior and that combining formal verification with UVM leads to greater robustness and efficiency in the validation process.
Abstract
This work presents a comparative study of formal and simulation-based hardware verification techniques within the context of digital systems. The analysis covers Formal Property Verification (FPV), Formal Equivalence Verification (FEV), Assertion-Based Verification (ABV), and the Universal Verification Methodology (UVM). A synchronous First-In-First-Out (FIFO) buffer is used as a case study to explore the practical application and effectiveness of each technique. The study highlights the strengths and limitations of each approach based on criteria such as coverage, computational cost, scalability, debugging capability, and level of automation. The results indicate that no single technique is universally superior and that combining formal verification with UVM leads to greater robustness and efficiency in the validation process. The work also discusses recent advancements in the field and the growing adoption of formal verification in the semiconductor industry.
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