BRAIN-AD: A Bit-Serial, ReRAm-Empowered Digital Processing-In-Memory Macro for Autonomous Driving

Abstract

Conventional processing-in-memory (PIM) architectures suffer from limited efficiency due to transistor-intensive adder trees and analog-to-digital converter (ADC) overhead. This work presents BRAIN-AD, a bit-serial, ReRAM-based digital PIM macro for energy-efficient autonomous driving assistance systems (ADAS). The proposed design integrates a compact 1-bit multiply-accumulate (MAC) unit combining a 3T1R Re-XNOR non-volatile bit-cell for in-memory multiplication with an area-efficient 10 T pass-transistor full adder for sequential accumulation. A 16 Kb (128 × 128) macro employs sparsity-aware power gating and supports scalable fixed-point computation from 1 to 16 bits via bit-serial execution. Post-layout simulations in 65 nm CMOS achieve peak throughput of 0.72 TOPS and 112 TOPS/W energy efficiency, providing approximately 1.8× higher throughput and 1.95× higher energy efficiency than state-of-the-art digital PIM designs. System-level evaluation using a quantised INT4 NVIDIA PilotNet model shows less than 2.5% accuracy degradation relative to the FP32 baseline. These results establish BRAIN-AD as a robust, scalable, and practical digital PIM solution for resource-constrained ADAS workloads. This work highlights digital ReRAM-based bit-serial PIM as a scalable and robust alternative to analog CIM for safety-critical edge-AI applications.