Comparative Analysis and Genetic Algorithm Optimization of Multi-Transistor FinFET SRAM Topologies for SNM, Leakage, and Delay Improvement at 18nm

Abstract

With continuous technology scaling, Static Random Access Memory (SRAM) faces significant challenges including increased leakage power, reduced stability, and higher delay. FinFET technology has emerged as a promising alternative to conventional CMOS technology due to its superior electrostatic control and reduced short-channel effects. This paper presents a multi-objective Genetic Algorithm (GA) optimization framework for 6T, 7T, 8T, 9T, and 10T SRAM architectures using 18nm FinFET technology. The proposed optimization methodology focuses on minimizing leakage power, dynamic power, read delay, and write delay while maximizing Static Noise Margin (SNM). Cadence Virtuoso and the Spectre simulator were used for transient, DC, and power analysis. Genetic Algorithm optimization was implemented using transistor sizing and fin-count optimization techniques. The optimized SRAM architectures demonstrated significant reductions in leakage and dynamic power at a reduced supply voltage (1 V versus 1.5 V), with lower noise margins and a mixed effect on propagation delay. Simulation results show that optimized 10T SRAM achieved the lowest leakage power while 9T SRAM exhibited the highest read stability.