Design and Verification of an optimized 32-bit pipelined multiplier for high performance computing
TL;DR
A novel 32-bit pipelined multiplier is designed aimed at achieving high throughput and low power consumption for VLSI applications and a linear Pipelining technique with flipflops is implemented to minimize critical path delay.
Abstract
Arithmetic operations are fundamental to digital signal processing systems, where multipliers often decide overall performance constraints. They are key components of many high-performance systems such as Microprocessors, FIR Filters, Digital Signal Processors etc. The most common way of performing signed multiplication in digital circuits is by using booth multipliers, but the existing algorithm has a drain on power consumption since it never coerces operations to the full precision. In this paper, a novel 32-bit pipelined multiplier is designed aimed at achieving high throughput and low power consumption for VLSI applications. Modified Booth Encoding (MBE) with Radix-8 and Wallace tree reduction for partial products reduction and along with a CLA adder for partial products addition is used. Furthermore, a linear Pipelining technique with flipflops is implemented to minimize critical path delay. The Register Transfer level (RTL) model was implemented using Verilog and synthesized using Xilinx Vivado. Performance analysis demonstrates the reduction of delay by 23% and power consumption by 61%.