A 28-nm Digital Transpose SRAM Compute-in-Memory Macro With Accurate/Approximate Dual Mode for Floating-Point Edge Training and Inference

MECA-CiM: A Shared-MicroExponent-aware Configurable Analog Compute-in-Memory Macro for Efficient Inference

SRAM-based compute-in-memory (CiM) accelerators have emerged as a promising approach for low-power inference in edge devices by alleviating data-movement overhead. However, existing CiM designs face a fundamental trade-off: integer-based CiM suffers from limited numerical accuracy, while floating-point CiM incurs substantial energy and area overhead due to complex exponent handling and peripheral circuits. This paper presents an analog CiM accelerator based on the SMX6 format, which extends the block floating-point (BFP) representation with a lightweight microexponent (μE) shared by pairs of values. By embedding μE-aware scaling directly into the analog MAC operation, the proposed design achieves improved numerical fidelity without introducing costly digital shift-and-align logic. To further address accuracy degradation caused by analog dynamic-range limitations, the accelerator supports configurable block granularity, allowing the accumulation range to be adaptively adjusted to match layer-wise activation distributions and ADC input constraints. Implemented in 28nm CMOS technology, the proposed SRAM-based ACiM achieves accuracy close to the FP32 baseline across diverse workloads, while delivering up to 54.19 TOPS/W energy efficiency and 4.66 TOPS/mm2 area efficiency. These results demonstrate that micro-exponent-aware analog CiM with configurable granularity is an effective and practical design point for energy-efficient edge inference.

Multi-Scheduling Crossbar Mapping and Design-Space Exploration of MAGIC-Based ReRAM Arithmetic Circuits for In-Memory Computing

Joint Multiplier–Adder Approximation with Flag-Based Error Recovery for BF16 Digital Compute-in-Memory

Digital computing-in-memory (DCIM) provides deterministic floating-point computation but incurs substantial area and power overhead from replicated mantissa multipliers and adder trees. This work proposes an error-recoverable BF16 DCIM arithmetic unit that jointly approximates a 2-bit multiplier and the first adder stage. For the 11 × 11 input, the multiplier outputs 0111 instead of the Baseline 1111, converting the error from +6 to −2 and fixing the product MSB to 0. This enables the first adder stage to be reduced from 4 bits to 3 bits. A lightweight flag detects the same error condition and is reused as a carry input for local compensation, avoiding a separate multi-bit correction circuit. Hierarchical design-space exploration selected the 0111 approximation with carry compensation at bit position 1. Transistor-level evaluation showed reductions of 14.81% in transistor count and 28.56% in average power relative to the Baseline. Across ResNet18, VGG16-BN, and AlexNet on CIFAR-10 and CIFAR-100, the Proposed scheme achieved the lowest BF16-referenced Layer NRMSE and Logit NRMSE among the evaluated Baseline, DIMC-S-derived, LSAC OR+SXAFA-derived, and Proposed schemes, while the Top-1 accuracy difference relative to the Baseline remained within −0.02%p to +0.12%p. These results demonstrate an improved hardware–accuracy trade-off without retraining or data rearrangement.

A Hardware-Error-Aware Time-Domain CIM Accelerator for AdderNet with Significance-Aware Dual-Mode DTC Encoding and Shared-Clock TDC Readout

Adder neural networks remove multiplication from convolution, yet their direct L1-distance datapath still requires subtraction, absolute-value generation, and wide accumulation. We address this cost by mapping the online L1 operation to minimum selection and time-domain accumulation. The proposed accelerator processes a 3×3×16 window for 16 output channels with 6-bit weights and activations. Each 6-bit minimum is divided into two 3-bit slices. A dual-mode digital-to-time converter (DM-DTC) encodes the most-significant slice in high-linearity (HL) mode and the least-significant slice in low-power (LP) mode. Readout is performed by a shared-clock time-to-digital converter (SC-TDC), in which one Gray-code time reference serves all paths while local latches preserve independent channel results. The training model reproduces code-dependent DTC nonlinearity, process–voltage–temperature variation, jitter, channel offset, TDC quantization, saturation, and scale mismatch. The architecture thereby combines significance-aware time encoding, channel-scalable readout, and hardware-aware adaptation. Post-layout simulations in 55 nm show that the 0.359 mm2, 13.7 Kb design operates at 0.7–1.2 V and 5–30 MHz, consumes 0.025–0.324 mW, and achieves 43.2–94.3 TOPS/W. The normalized figure of merit is 6.01–13.09 POPS/W·bit2. On CIFAR-10/ResNet-20, hardware errors reduce the baseline accuracy from 92.71% to 86.26%; error-aware training achieves 91.53%.

REF-CIM: A 40-nm Non-Ideality Tolerant and Energy Efficient RRAM Compute-in-Memory Macro With Configurable Precision for Edge AI

Compute-in-Memory (CIM) based on resistive random access memory (RRAM) offers significant advantages in energy efficiency and parallelism, making it a promising solution for accelerating neural networks. However, the computational accuracy, energy efficiency, and flexibility of current CIM chips are still challenged by practical issues such as device and circuit-level non-ideality and the high overhead of peripheral circuits, which remain inadequately addressed in existing designs. To address these challenges, this work proposes REF-CIM, a 40nm robust, energy efficient and flexible RRAM- CIM macro that achieves non-ideality tolerance, high energy efficiency and configurable precision, featuring: 1) a complementary multi-bit input unit (CMIU) with symmetric bit-line access; 2) a proportional current-scaling clamp circuit (PCSC); 3) a distributed tree-based sparse analog-to-digital converter (DTS-ADC); and 4) a configurable multi-mode deployment scheme for supporting diverse neural network precisions. The performance of the proposed macro is evaluated through chip measurements, considering non-ideal effects such as IR-drop, device variation, and analog circuit noise. Simulation results calibrated with measurement data demonstrate a peak energy efficiency of 29.1 TOPS/W@8bIN/8bW/16bOUT, with classification accuracy reaching 92% on the CIFAR-10 dataset under 10% device variation.

A Schematic-Level Digital Near-Memory Computing Architecture Utilizing 1T3R Memristor Arrays and Pipelined MAC for Pattern Recognition

The traditional von Neumann architecture faces a severe memory wall bottleneck in modern data-intensive artificial intelligence applications. Memristor-based Computing-in-Memory (CIM) is a promising approach to reduce data movement, but conventional analog CIM remains vulnerable to read noise, sneak path currents, device variation, and the area and power overhead of high-resolution Analog-to-Digital Converters (ADCs). This work presents a schematic-level digital near-memory computing architecture based on a 1-Transistor-3-Resistor (1T3R) bit-slicing scheme for 3-bit signed weight storage. Each weight is mapped to three binary memristor states using two's complement representation, and the sensed digital outputs are processed by a low-bit pipelined Multiply-Accumulate (MAC) and Rectified Linear Unit (ReLU) backend. This design avoids high-resolution analog current readout and shifts the main computation to compact digital logic. The memristor array, write-inhibit and read control scheme, and digital processing blocks are implemented and functionally verified at schematic-level in Cadence Virtuoso using the open-source SkyWater 130 nm Process Design Kit (PDK) at a nominal 1.8 V supply. For system evaluation, a Python simulation framework is developed to incorporate the same low-bit quantization, signed weight mapping, finite bit digital arithmetic, and modeled device nonidealities. Hardware-aware simulations on Modified National Institute of Standards and Technology (MNIST) indicate that the proposed architecture can maintain functional classification capability under 3-bit weight and 2-bit input constraints. The reported macro power, performance, and area values are first-order projections from schematic simulations and scaling assumptions. Layout implementation, parasitic extraction, and post-layout validation remain future work.