Multi-Scheduling Crossbar Mapping and Design-Space Exploration of MAGIC-Based ReRAM Arithmetic Circuits for In-Memory Computing

Robust Hybrid Computing-in-Memory System Based on 2T-2C and 4T-2C FRAM Cells

This paper proposes a computing-in-memory (CiM) architecture based on a hybrid 2T-2C/4T-2C ferroelectric random-access memory (FRAM) array that provides ADC-free bitwise computing with binary inputs and outputs, reducing peripheral-circuit overhead and power consumption.

FPGA Architectures to Enable Concurrent LUT and Adder Chain Usage

This work proposes Double-Duty, a logic block architecture that decouples LUTs and adder chains by augmenting four extra inputs of the logic element to bypass LUTs and directly drive the adders.

Design of a 1-bit Adder/Subtractor Using Multi-Gate Transistors for High Speed and Low Power Applications

The results establish the feasibility of the proposed MGFET-based programmable logic architecture for compact, high-speed, and low-power arithmetic circuits for future programmable nanoscale digital systems.

Adaptive Precision Hierarchical Vedic Multiplier with CSA-Based 64-Bit Optimization for Low-Power FPGA Applications

In this paper, an energy-efficient Vedic multiplier design is presented through runtime-adaptive hierarchy. In the proposed architecture, the Urdhva-Tiryakbhyam Vedic algorithm has been implemented recursively from 2x2 to 32$\times$32 bit multiplication in a modular hierarchical fashion. In addition, the multiplier has...

A Power-Aware 64-bit Hybrid Multiplier using Vedic Arithmetic and Wallace Tree for High-Performance Filter Applications

Design Space Exploration of In-Memory Computing Implementations for Discrete Fourier Transform

A comprehensive hardware-aware design framework for systematically mapping algorithmic workloads onto IMC architectures, using the discrete Fourier transform (DFT) as a case study and a novel mapping scheme that reduces energy consumption per computation by 53% compared with conventional mapping techniques is introduce...