TL;DR
This review bridges the gap by categorising and evaluating RISC-V advancements in key domains, including processor cores, system-on-chip architectures, ecosystem growth, software support, and hardware development platforms.
The exponential growth of artificial intelligence (AI) applications in edge devices, embedded systems, and data centers has intensified the demand for efficient and scalable processor architectures. This paper provides a comprehensive comparative analysis of RISC-V and ARM architectures in AI applications, examining th...
All of these factors contribute to improved performance, lower latencies, and optimized use of resources and therefore, place RISC-V processing architectures as being the preferred architecture for the Intelligent Computing Solutions of the future.
The Chapel programming language recently added support for the RISC-V architecture. Here we discuss what changes were needed for Chapel to work on RISC-V as well as lessons learned from the porting process. We use some of Chapel's extensive benchmark suite to gain further insight into the suitability of the RISC-V arch...
It is demonstrated that for embedded workloads, a 4-lane, 128-bit vector unit with a 32-bit bus offers the best area-performance trade-off, and a design-space exploration of the vector unit is presented.
The significance of compilers, how to optimize them, and a thorough comparison between the GNU compiler collection (GCC) and low-level virtual machine (LLVM) compilers are discussed.
Puppy, a RISC-V-based System-on-Chip (SoC) targeting energy-efficient edge artificial intelligence (AI) applications, is presented as a validated and accessible solution for intelligent embedded systems.
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