Layered semiconductors offer a promising route beyond conventional silicon technology but face challenges in integrating high-k dielectrics due to their dangling-bond-free surfaces. Here, we report a direct atomic layer deposition approach, termed HALO (High-dose precursor immersion, Adsorption enhancement, and Low-temperature Oxide improvement) ALD, enabling uniform HfO2 growth on two-dimensional (2D) materials without surface functionalization. The HALO process improves nucleation and interface quality, yielding smooth high-k films (∼0.1 nm roughness). MoS2 dual-gate field-effect transistors (FETs) exhibit an equivalent oxide thickness of 0.83 nm, a subthreshold swing of 80 mV dec–1, and breakdown fields up to 9 MV cm–1. Reliability studies, including bias stress and thermal tests, confirm stable device operation. This approach further enables conformal high-k integration in gate-all-around structures, providing a scalable pathway for three-dimensional (3D) integration of 2D electronics.
This study reports a gate stack composed of an ultrathin epitaxial hexagonal aluminum nitride (h-AlN) interfacial layer (IL) deposited by plasma-enhanced atomic layer deposition (PEALD) between hafnium oxide (HfO2) and a monolayer tungsten disulfide (WS2) channel. The inherently inert surfaces of two-dimensional (2D)...
We report atomic layer deposition-grown indium–tungsten–tin oxide (IWTO) thin-film transistors that effectively circumvent the conventional on-current–threshold voltage (ION–VTH) trade-off in atomically thin oxide semiconductors. A W/Sn co-engineered IWTO channel is developed by systematically varying the W concentra...
Tsung-Che Chiang, Yi-De Tsai, Shi Guo et al.· ACS Applied Electronic Mater...· 0 citations
Two-dimensional (2D) transition metal dichalcogenides (TMDs) offer a promising pathway for next-generation electronics due to their exceptional electrical characteristics at atomically thin thickness. Nevertheless, the realization of high-quality p-type 2D-FETs remains a significant challenge for CMOS device integratio...
Jonggyu Choi, Hayoung Kim, Seungsoo Kim et al.· Science Advances· 0 citations
Achieving high electrical quality gate dielectrics for thin-film transistors atop flexible substrates is a challenge due to thermal constraints imposed by the soft and sensitive substrates. This study examines a multitude of deposition pathways using rigid metal–insulator–metal (MIM) capacitors to discern effective s...
Amit Tewari, Antti Tukiainen, Jyoti Kandpal et al.· ACS Applied Electronic Mater...· 0 citations
Aggressive channel thickness scaling to the sub-2 nm regime is essential for strengthening electrostatic gate control in monolithic three-dimensional electronics, but it causes severe carrier depletion and transport degradation in In2O3 thin-film transistors (TFTs). Here, we demonstrate enhancement-mode TFTs with 1.5 n...
Seung Ho Ryu, S. Kim, Taikyu Kim et al.· Applied Physics Letters· 0 citations
The atomically smooth surfaces of two-dimensional (2D) nanomaterials minimise scattering-induced carrier-transport degradation. However, this same attribute poses a major challenge for integrating 2D materials with high-quality dielectrics at sub-nanometre equivalent oxide thickness (EOT) through direct growth. Here we...
Sun-Leng Wong, Fu-Fei An, Yu Wu et al.· Nature Communications· 0 citations
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