Noise-aware fine-tuning as a hardware noise margin: Cross-layer co-design for robust low bit RRAM in-memory computing toward space-borne edge inference

Abstract

Resistive Random Access Memory (RRAM)-based Computing in-memory (CIM) accelerators promise orders of magnitude energy savings for space-borne edge inference. At the low bit precision imposed by tight power budgets, however, device-level conductance noise competes directly with the quantization signal margin. While conventional Quantization-Aware Training (QAT) can adapt neural networks to low bit hardware, it remains insufficient against physical conductance fluctuations, often leading to severe accuracy degradation in regression tasks. We therefore introduce noise-aware fine-tuning as a cross-layer robustness primitive, a three-stage pipeline (PQAT-FT) in which sparse regularization and noise injection reshape the weight distribution to carve unused conductance headroom, interrupting layer-by-layer error propagation. Measured on a fabricated 8K RRAM CIM test chip over five programming rounds (mean +/- SD), PQAT-FT consistently reduces the 4-bit inference error across both bounded and unbounded activations, lowering the RMSE for Tanh, Sigmoid, Leaky ReLU, and ReLU by 64.2%, 18.7%, 25.3%, and 36.8%, respectively. Notably, Tanh exhibits the largest relative improvement over its QAT baseline. These findings establish noise-aware fine-tuning as an effective primitive for low bit RRAM CIM across the four activations and bit widths tested on this hardware platform, toward future space-borne edge systems.