Chip-Agnostic Hardware-Aware Training for ADC-Efficient BNNs in SOT-MRAM Crossbars
TL;DR
A SPICE-based hardware-aware training framework that injects end-to-end crossbar non-idealities directly into the BNN training flow and supports both chip-agnostic and chip-specific training for robust, generalized deployment across varying hardware instances without per-chip retraining.
Abstract
Analog in-memory computing using SOT-MRAM crossbars is a promising approach for energy-efficient acceleration of Binary Neural Networks (BNNs). However, analog-to-digital converters (ADCs) remain a major latency and power bottleneck, forcing a direct trade-off between ADC precision and model accuracy. Furthermore, crossbars and their peripherals suffer from process variations, introducing noise that further degrades accuracy. To address this, we propose a SPICE-based hardware-aware training framework that injects end-to-end crossbar non-idealities directly into the BNN training flow. Our methodology supports both chip-specific training for precise device-level adaptation, and a novel chip-agnostic training for robust, generalized deployment across varying hardware instances without per-chip retraining. On ImageNet, scaling down to 4-bit ADCs reduces inference energy by ~30%. Despite this aggressive quantization and compounded hardware noise, our chip-agnostic and chip-specific frameworks bridge the hardware-software gap, limiting the Top-1 accuracy drop of a 4-bit MeliusNet22 to 2.7% and 0.9%, respectively, compared to an FP32 software baseline.