Sep 2026· IEEE Transactions on Very Large Scale Integration (vlsi) Systems· Vol 34, pp. 2924-2934· 0 citations· 39 references
Abstract
The growing demand for efficient deep-learning inference on edge platforms requires hardware that is both energy-efficient and practically implementable. This work presents a 16-Kb all-digital static random-access memory (SRAM)-based compute-in-memory (CIM) macro for low-bit CNN inference, featuring a hierarchical adder-tree-based accumulation architecture. The design integrates a nor-enabled SRAM compute cell, column-wise rearrangement network, sparsity-aware compression, and multistage hierarchical accumulation within a 64-bank $64 \,\, \times \,\, 4$ architecture, enabling scalable bit-serial processing and utilization-aware mapping. Implemented in 65-nm CMOS, the macro achieves 8.19 TOPS effective throughput at 1.0 V and a peak energy efficiency of 586 TOPS/W at 0.9 V under practical operating conditions. Hardware-compatible CNN mapping is demonstrated using LeNet-5, VGG-8, and ResNet-8. The design achieves 98.1% and 72.3% accuracy on MNIST and CIFAR-10, respectively, with 1-bit activations and 4-bit weights, while 4-bit configurations on deeper networks show only 3%–4% degradation from FP32 baselines. CNN inference is evaluated using a hardware-compatible post-training quantization (PTQ) flow without retraining. These results demonstrate that the proposed SRAM-CIM architecture provides an efficient and scalable accumulation solution with a practical tradeoff among throughput, energy efficiency, and implementability for edge-oriented deep neural network (DNN) inference.
Edge intelligence applications demand high-throughput and energy-efficient hardware accelerators under strict power, latency, and resource constraints in real-time environments. Conventional compute-centric architectures rely heavily on sequential multiply-accumulate (MAC) operations and frequent off-chip memory access, resulting in high energy consumption, increased latency, and bandwidth bottlenecks. These limitations become more pronounced as neural network models scale in size and complexity. While Ternary Content-Addressable Memory (TCAM) offers an alternative through parallel associative search and constant-time pattern matching, it suffers from excessive power consumption and limited adaptability due to continuous match-line activation. This work proposes a hybrid SRAM-TCAM memory-centric deep neural network (DNN) architecture that integrates three tightly coupled subsystems. First, a two-layer autoencoder with ReLU activations compresses 128-bit input feature vectors to 32-bit latent codes, achieving a compression ratio η=4×\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\eta = 4\times $$\end{document} and a 75%\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$75\%$$\end{document} BRAM saving. Second an on-chip dual-port BRAM data-locality buffer exploits the compressed representation to eliminate inter-layer off-chip DRAM accesses in the critical inference path. Third, a 256×32\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$256 \times 32$$\end{document}-bit Ternary Content-Addressable Memory array provides O(1) parallel associative inference. A software-only Genetic Algorithm (GA) with Roulette Wheel Selection (RWS) optimizes TCAM configuration offline prior to FPGA deployment; the converged 8,480-bit chromosome is loaded once at startup and remain static during inference, adding zero dynamic power overhead. The proposed architecture, implemented on a Xilinx Artix-7 FPGA, achieves a 42.3%\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$42.3\%$$\end{document} reduction in power compared to a conventional MAC-based baseline (120.5 mW vs. 208.7 mW), an end-to-end throughput of 108.47 Mops reflecting steady-state pipelined operation at 108.47 MHz (2.42×\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$2.42\times $$\end{document} speedup), and an inference accuracy of 95.3%\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$95.3\%$$\end{document} – a 1.5%\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$1.5\%$$\end{document} degradation attributable to quantization, evaluated on the benchmark dataset. Power figures are obtained from the Vivado Power Estimator tool (post-implementation) at nominal supply voltage of 1 V. These results demonstrate an efficient and scalable solution for next-generation edge AI inference systems.
Vandana Thakur, V. More, Abhishek Bhatt· Journal of King Saud Univers...· 0 citations
Spiking Neural Networks (SNNs) are promising for low-power edge intelligence due to their event-driven computational model. However, their hardware implementation poses challenges in terms of energy efficiency and memory access overhead. This paper presents an SRAM-based near-memory computing neuromorphic core supporting 256 leaky integrateand-fire neurons and 65,536 synapses. Synthesized in 40 nm low-power CMOS, the core occupies 0.3 mm2, operates at 70 MHz, consumes 7.67 mW, and achieves $\mathbf{0 . 6 4} \mu \mathbf{J}$ per inference and 0.22 pJ per synaptic operation. A five-core SNN system reaches 96% accuracy and 11 kFPS throughput on the MNIST dataset. A complete System-on-Chip was fabricated using SkyWater 130 nm CMOS via the eFabless multi-project wafer platform, including a small programmable computing core interfaced with a RISC-V processor via the Wishbone bus as a standard memory-mapped peripheral. This core implements 32 neurons and 8,192 synapses, and occupies 0.33 mm2 within a total chip area of 7 mm2. Firmware was loaded onto the SoC to verify the functionality of the full hardware-software system. Measurement results confirm improved energy efficiency and real-time performance, highlighting the suitability of SRAM-based architectures for ultra-low-power neuromorphic computing at the edge.
Linh Nguyen-Phuong, Chi Hoang Phuong, Anh Ong-Tung et al.· IEEE International Conferenc...· 0 citations
Conventional processing-in-memory (PIM) architectures suffer from limited efficiency due to transistor-intensive adder trees and analog-to-digital converter (ADC) overhead. This work presents BRAIN-AD, a bit-serial, ReRAM-based digital PIM macro for energy-efficient autonomous driving assistance systems (ADAS). The proposed design integrates a compact 1-bit multiply-accumulate (MAC) unit combining a 3T1R Re-XNOR non-volatile bit-cell for in-memory multiplication with an area-efficient 10 T pass-transistor full adder for sequential accumulation. A 16 Kb (128 × 128) macro employs sparsity-aware power gating and supports scalable fixed-point computation from 1 to 16 bits via bit-serial execution. Post-layout simulations in 65 nm CMOS achieve peak throughput of 0.72 TOPS and 112 TOPS/W energy efficiency, providing approximately 1.8× higher throughput and 1.95× higher energy efficiency than state-of-the-art digital PIM designs. System-level evaluation using a quantised INT4 NVIDIA PilotNet model shows less than 2.5% accuracy degradation relative to the FP32 baseline. These results establish BRAIN-AD as a robust, scalable, and practical digital PIM solution for resource-constrained ADAS workloads. This work highlights digital ReRAM-based bit-serial PIM as a scalable and robust alternative to analog CIM for safety-critical edge-AI applications.
Ankit Kumar Tenwar, Mukul Lokhande, A. Teman et al.· IEEE transactions on nanotec...· 0 citations
SRAM-based compute-in-memory (CiM) accelerators have emerged as a promising approach for low-power inference in edge devices by alleviating data-movement overhead. However, existing CiM designs face a fundamental trade-off: integer-based CiM suffers from limited numerical accuracy, while floating-point CiM incurs substantial energy and area overhead due to complex exponent handling and peripheral circuits. This paper presents an analog CiM accelerator based on the SMX6 format, which extends the block floating-point (BFP) representation with a lightweight microexponent (μE) shared by pairs of values. By embedding μE-aware scaling directly into the analog MAC operation, the proposed design achieves improved numerical fidelity without introducing costly digital shift-and-align logic. To further address accuracy degradation caused by analog dynamic-range limitations, the accelerator supports configurable block granularity, allowing the accumulation range to be adaptively adjusted to match layer-wise activation distributions and ADC input constraints. Implemented in 28nm CMOS technology, the proposed SRAM-based ACiM achieves accuracy close to the FP32 baseline across diverse workloads, while delivering up to 54.19 TOPS/W energy efficiency and 4.66 TOPS/mm2 area efficiency. These results demonstrate that micro-exponent-aware analog CiM with configurable granularity is an effective and practical design point for energy-efficient edge inference.
W. Han, Dohyun Kim, Jihoon Park et al.· Proceedings of the ACM/IEEE...· 0 citations
To address the “memory wall” bottleneck in von Neumann architectures, this paper proposes novel FeFET-embedded Complementary Metal-Oxide-Semiconductor (CMOS) adders for efficient Processing-in-Memory (PiM). Leveraging the tunable threshold voltage of Ferroelectric Field-Effect Transistors (FeFETs), the design enables Analog-to-Digital Converter (ADC)-free arithmetic operations by integrating data storage and logic within a hybrid circuit structure. We detail the implementation of FeFET-embedded NOT-AND (NAND) and Exclusive OR (XOR) gates to construct half-adders, full-adders, and a scalable 4-bit adder. Operating in distinct write and calculation modes, the architecture performs in-memory addition without complex signal converters. Simulation Program with Integrated Circuit Emphasis (SPICE) simulations validate the functional correctness, low energy consumption and low latency of the proposed design. The proposed FeFET-PiM adder achieves an ultra-low computational energy consumption of 0.657 fJ/bit and a latency of merely 48.6 ps. These figures represent a significant reduction compared to analog PiM adders, demonstrating its substantial potential for low-power advanced electronic devices.
Chen He, Wei Li, Jianjun Li et al.· Journal of Physics, Conferen...· 0 citations
The conventional von Neumann architecture, constrained by the memory and power walls arising from the separation of storage and computation, faces significant limitations in computational efficiency and energy consumption. To address these challenges, this paper proposes a computing-in-memory (CiM) architecture based on a hybrid 2T-2C/4T-2C ferroelectric random-access memory (FRAM) array. The proposed architecture performs majority-based bitwise computation by simultaneously activating multiple word lines, enabling AND and OR operations in conventional 2T-2C FRAM cells. Selectively embedded 4T-2C FRAM cells further provide in-array inversion, extending the supported functions to NOT and functionally complete Boolean logic. The architecture also supports full-adder operations and stores input operands, intermediate data, and output results within the same FRAM subarray, thereby reducing data movement. Moreover, the architecture provides ADC-free bitwise computing with binary inputs and outputs, reducing peripheral-circuit overhead and power consumption. The internal computation, nevertheless, relies on analog charge sharing and differential sense-amplifier resolution. HSPICE simulations indicate PVT-evaluated sensing stability and computational efficiency under the evaluated conditions. The bit-line voltage difference reaches 337 mV under triple-row activation and 214 mV under quintuple-row activation, with the former being 5.2 times that of the reported DRAM implementation used for comparison. At 3.3 V, process–voltage–temperature (PVT) simulations show that the maximum deviation of ΔV from its mean value remains below 4.62% across the evaluated process corners and temperatures from −40 °C to 125 °C. Simulations of the 8 × 8 FRAM CiM compute-array circuit model yield an energy consumption of 1.94–3.46 pJ/bit and a calculation latency of 0.599–1.167 ns for the supported bitwise operations, corresponding to a 4.86×–5.90× reduction in energy consumption compared with the reported DDR3-based design. The architecture also supports parallel processing and mitigates data loss associated with destructive FRAM readout through an in-array replication mechanism. Finally, an 8 × 8 hybrid FRAM CiM prototype was fabricated in a 180 nm CMOS process as a physical implementation of the proposed hybrid architecture, and its basic array functionality was verified.
Chen He, Jianjun Li, Wei Li et al.· Electronics· 0 citations
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